1. Field of Invention
The present invention relates generally to semiconductor memories and particularly to controlling a DRAM array.
2. Description of Related Art
Dynamic RAM (DRAM) is presently used as the main memory of most computer systems and accounts for more than half of the global semiconductor memory market. DRAM operates at a much lower frequency than do modern microprocessors, and therefore limits the throughput of such microprocessors. Although SRAM is much faster than DRAM, the high cost of SRAM precludes its use as the main memory of a computer system. Accordingly, there is a need to increase the speed of DRAMs so as to close the gap between DRAM and microprocessor speeds.
FIG. 1 shows a system 1 having a conventional DRAM 10 and an associated memory controller 20. The DRAM 10 includes a DRAM cell array 11, a row decoder 12, latches 13, and a multiplexer (column decoder) 14. The memory controller 20 includes an address queue 21, registers 22, a strobe control circuit 23, and a refresh circuit 24. When the DRAM 10 and associated controller 20 are powered up, frequency values for the row address strobe and column address strobe, as well as the period for refresh operations, are loaded into registers 22 from a ROM BIOS 30. The DRAM 10 is accessed by an associated central processing unit (CPU) 40 via the controller 20. The CPU 40 provides input addresses specifying the location of a cell desired to be read from or written to on input address pins A[0:n]. The addresses are then queued in the address queue 21. The row address of a selected cell is forwarded to the row decoder 12 on the falling edge of the row address strobe ({overscore (RAS)}) signal. The contents of all cells within the row specified by the row address are latched into corresponding latches 13. The column address of the selected cell is forwarded to the multiplexer 14 on the falling edge of a column address strobe ({overscore (CAS)}) signal. The multiplexer 14 selects latches 13 corresponding to the cell identified by the column address. During a read operation, the latch values are provided as output on data pins D[0:n]. During a write operation, input data provided on the data pins D[0:n] is written to the selected latches 13. The row of data stored in the latches 13 is subsequently written back to the selected row of cells in the array 11 during a well known refresh operation via the refresh circuit 24.
The {overscore (RAS)} and {overscore (CAS)} signals are generated by the strobe control circuit 23 according to a system clock residing therein. Frequency values for the {overscore (RAS)} and {overscore (CAS)} signals, as well as the interval between refresh operations, i.e., the refresh period, are forwarded from the ROM BIOS 30 to the memory controller 20 upon power up and thereafter stored in the registers 22, as mentioned above. The default {overscore (RAS)} and {overscore (CAS)} signal frequencies and the refresh period stored within the ROM BIOS 30 are typically conservative so as to avoid charge loss in the DRAM cells and to ensure proper timing. Thus, although ensuring safe DRAM operation, these default frequency values do not result in optimum DRAM performance. For instance, while most DRAMs are specified to refresh the cells approximately every 20 ms, as directed by their ROM BIOS chips, the capacitor cells of the DRAM array may retain charge for up to 2 seconds, perhaps longer. Refreshing the cells more frequently than necessary for proper operation, i.e., every 20 ms as opposed to every 2 seconds, not only results in unnecessary power consumption but also unnecessarily consumes valuable clock cycles. Accordingly, using conservative, static values for the refresh period and for the frequency of the {overscore (RAS)} and {overscore (CAS)} signals undesirably limits DRAM performance.
An apparatus and method are disclosed which greatly enhance DRAM operation. In accordance with the present invention, an adaptive memory control technique determines optimal values for certain DRAM parameters such as, for instance, the refresh period and for the row and column address strobe signal frequency. Default values for all but a selected one of the DRAM parameters are provided to the DRAM""s memory controller, and an aggressive value for the selected parameters is provided to the memory controller. A binary test pattern is written to the DRAM array, read during a subsequent read operation following a refresh operation, and then compared to the original test pattern. If there is a match, the 1""s complement of the test pattern is written to the array and then compared with the original 1""s complement pattern as described above. If there is a match, the process is repeated using a more aggressive value for the refresh period. Conversely, if at any point the above-described comparison does not result in a match, a more conservative refresh period is used. Thus, the optimal value for the selected parameter is homed in on with each write, read, and compare sequence. Once the optimal value for the selected parameter is determined, the above-described process may be used to determine the optimal value for another DRAM parameter, e.g., the row and column address strobe frequency.